| 摘要 |
<p>A first MOS (metal-oxide-semiconductor) NOR-gate device feeding a second MOS NOR-gate device feeding an MOS output load device is arranged to yield a three output level buffer circuit, that is, a circuit whose output to a common data bus line can be "high" ("1"), "low" ("0"), or of very high impedance ("floating"). Each NOR-gate contains a low ("load") depletion mode MOS transistors (M3, M5) and a high ("driver") enhancement mode (M4, M"4, M6, M"6) MOS; the output load device contains an output driver enhancement mode MOS transistor (M2) and an output load MOS transistor (M1) having a threshold intermediate that of the depletion mode and enhancement mode M0S transistors. In this manner, only a single voltage source VDD, of typically about +5 volts in N-MOS integrated circuit technology is required to power the buffer circuit completely. </p> |
