| 摘要 |
PURPOSE:To minimize a non-volatile memory by integrating a plurality of memories each having n<+>-type layers for surrounding p-type source and drain regions and a floating gate using an n-type silicon substrate. CONSTITUTION:n<+>-Type layers 42, and p-type source and drain regions 43, 44 are formed in an n-type substrate 41, and a floating gate 45 is formed in an oxide film 46 on the substrate 41. According to this configuration even if the layer 43 is in higher density, the interval between the layers 42 can be reduced, threshold voltage can be reduced by utilizing its short channel, operating margin can be increased with respect to the charge injection amont to thus eliminate reading region as provided in the conventional one, and respective cells can be reduced in its size. Accordingly, the entire circuit thus integrated can be remarkably minimized. |
