发明名称 |
METHOD OF FABRICATING SEMICONDUCTOR DEVICE |
摘要 |
A method for reducing parasitic capacitance in semiconductor devices, particularly for the removal of raised portions of conductive layers overlying and capable of being capacitively coupled to other conductors in semiconductor memory integrated circuits. The method provides for the application of a masking or photoresist layer over the surface of a substrate containing portions of a conductor to be removed such that the masking layer completely covers the conductor. Next a uniform thickness of the masking layer is removed to expose only the raised portions of the conductor which are subsequently selectively etched through the remainder of the masking layer. Application of the method to a manufacturing process for a dynamic MOSFET memory array is also described in which bit sense line capacitance is substantially reduced. |
申请公布号 |
JPS5591158(A) |
申请公布日期 |
1980.07.10 |
申请号 |
JP19790134316 |
申请日期 |
1979.10.19 |
申请人 |
IBM |
发明人 |
UENDERU FUIRITSUPU NOOBURU JIY;RICHIYAADO ARAN YUNISU |
分类号 |
H01L27/10;G11C11/34;H01L21/31;H01L21/3105;H01L21/3213;H01L21/70;H01L21/768;H01L21/8242;H01L23/52;H01L23/522;H01L27/108 |
主分类号 |
H01L27/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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