| 摘要 |
A circuit which efficiently controls the refresh operation of a dynamic memory. The refresh control circuit operates such that a dynamic memory (28) coupled to a processing means responds to a memory access signal (BMREQ) for a read/write operation and a first refresh control signal (BMREF) for a memory refresh operation. First circuits (30, 32) provide a second periodic refresh control signal (REFREQ), and second circuits (34, 40) refresh the memory under the control of either of the first (BMREF) or second (REFREQ) refresh control signals. A third circuit (20) responsive to the memory access signal (BMREQ) and the second refresh control signal (REFREQ) awards priority of access to the memory (28) in accordance with the first active signal which it receives. A fourth circuit (20) puts the processing means in a hold condition when priority is awarded to the second refresh control signal (REFREQ). In a power down condition a (BRST) signal enables gates (42) having a battery back up to permit the dynamic memory to be refreshed. |
