| 摘要 |
PURPOSE:To eliminate the delay time caused by generation of the check bit and thus to reduce the writing cycle time by preventing the time to generate the check bit from being added to the writing cycle time of the memory device. CONSTITUTION:When the writing address and the data are transferred to registers 3 and 4 respectively from the CPU, the data is transferred to generator 5 from register 4 to generate the check bit corresponding to the data. At the same time, the data is written to the fixed address of memory part 1, and the check bit at the preceding data writing time is written into memory part 2 via register 6. And with application of the reading address from the CPU, both the data and the check bit are read out of each memory part to be supplied to error check circuit 11 and register 13. And thus the error, if any, is corrected and then transferred to the CPU from register 13. |
