| 摘要 |
A process for forming a CIS (conductor-insulator-semiconductor) integrated circuit having one or more non-memory field-effect transistors, and one or more polysilicon resistors and/or polysilicon conductors. A single mask and implant sequence is used to establish the threshold voltage of the field-effect transistor and the resistance (conductance) of the polysilicon components. The polysilicon components are formed to predetermined sizes, as needed, so that the threshold-determining implant provides the desired polysilicon resistance value(s).
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