PROCESS ADAPTED TO THE MANUFACTURE OF D-RAM

摘要

The method is concerned with 1 transistor- 1 capacitor D-RAM cell having dual multicrystallic silicon electrode structure. The method comprises a 1st process for forming a channel stop region (18) by boron injection, a 2nd process for forming a field oxidization layer on the channel stop region, a 3rd process for forming a starage capacitor, a 4th process for foming anti α -particle barrier, a 5th process for forming 2nd polysilicon layer (26), a 6th process for forming a minifield oxidized layer (30), a 7th process for injecting the impurity, a 8th process for forming source (37) and drain region (38), and a 9th process for forming protective layer and alluminium beat line (42).