| 摘要 |
PURPOSE:To make alignment of individual portions easy and to readily manufacture highly integrated memories by utilizing complete or incomplete V grooves used for gates or isolation. CONSTITUTION:An inversely-conductive semiconductor layer 2 is formed on a conductive-type semiconductor substrate 1. Regions 3a-3d whose conductivity is the same as that of the substrate 1 are partially formed on the surface of the semiconductor layer 2. Complete V grooves 4a-4c and incomplete V grooves 4d- 4e, which are surrounded by regions 3a-3d, and whose bottoms reach the inside of the substrate 1, are further formed. Insulating gates 6a, 6b, 6c and 6d are provided on said grooves. The first FET is formed by the semiconductor layer 2, the substrate 1, and the semiconductor layers 2a-2d on which regions 3a-3d are formed; and the second FET is formed by the substrate 1, the semiconductor layers 2a-2d, and the regions 3a-3d. The semiconductor layers 2a-2d which are isolated from the surrounding portion, on which the regions 3a-3d are formed, are made to be an electric-charge storage region. |
