发明名称 DATA TRANSMITTER CIRCUIT
摘要 PURPOSE:To make it pissible to accomplish data transmission of a terminal equipment without keeping data transmission at a low speed side in a queue by interrupting data transmission at a high speed side while the low-speed data transmission is in process. CONSTITUTION:Processing part 10 of a terminal equipment fulfilling low-speed and high-speed data transmission processes has micro-computer 30 and is connected to series-parallel interchange circuit 36 for low-speed data transmission and series- parallel interchange-circuit 38 for high-speed data transmission. On the basis of a clock generated by clock circuit 40, circuit 36 performs data transmission and reception to output transmission in-execution indication signal 44, indicating that low- speed data transmission is in process, to clock circuit 42. Further, the other circuit 38 performs data transmission and reception on the basis of a clock generated by circuit 42 under the control of signal 44. Consequently, the high-speed data transmission process is interrupted during the period of the low-speed data transmission, but the lowering of its transmission rate is extremely slight. Therefore, the high-speed transmission of data can be carried out.
申请公布号 JPS5577259(A) 申请公布日期 1980.06.10
申请号 JP19780150073 申请日期 1978.12.06
申请人 HITACHI LTD 发明人 SUGIMOTO NORIHIKO
分类号 H04L29/08;G06F17/40;H04L25/05 主分类号 H04L29/08
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