Multi-port ram structure for data processor registers.

摘要

A data processor having a multi-port storage circuit for storing a binary logic state and having first and second terminals for providing a differential output signal representative of the binary logic state which is stored. A first and second pair of MOSFET devices selectively couple the first and second terminals to a first and second pair of conductors (130, 132) for sensing the binary logic state represented by the differential output signal.