发明名称 |
Address converter |
摘要 |
An address converter for decoding a multi-bit binary address has a binary adder to provide a logic subtraction of binary bit information introduced by a plurality of manually settable switches from a predetermined number of most significant binary bits in an address signal, an address-decode circuit for receiving an output signal from the adder and the next order of magnitude of the binary bits in the address signal and a plurality of system subunits which receive an output signal from the address-decode circuit and the remaining least significant bit information in the address signal to access the subunits according to the address signal and the switch settings in a predetermined order.
|
申请公布号 |
US4205390(A) |
申请公布日期 |
1980.05.27 |
申请号 |
US19780945444 |
申请日期 |
1978.09.25 |
申请人 |
HONEYWELL INC |
发明人 |
ISHIKAWA, TERUO;MATSUMOTO, TATEO;SAKURAI, KIYOSHI |
分类号 |
G06F12/06;(IPC1-7):G06F5/00;G06F13/00 |
主分类号 |
G06F12/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|