发明名称 SEMICONDUCTOR MEMORY CIRCUIT
摘要 <p>PURPOSE:To perform a protection operation completely by adding an FF circuit, which is reset at a power supply time and is set after a prescribed time, and an AND circuit. CONSTITUTION:When power is supplied at time t1, FF14 is reset, and output Q is logical level ''0''. Therefore, the output of AND gate 15 becomes logical level ''0''. Meanwhile, the voltage at terminal 16 rises by the time constant of resistance 17 and capacitor 18. Consequently, if the time constant above is selected that FF14 can be set after the voltage at terminal 2 reaches a set value, for example, at time t2, the output of FF14 is logical level ''1'' at time t2, and the rewrite read output of control circuit 4 to semiconductor memory 3 and the Q output of FF14 are subjected to AND gate by AND circuit 15 to generate an output in circuit 15. That is, the output of circuit 4 is inhibited completely from time t1 to time t2, and disadvantage of applying false signals, which disturb contents of memory 3, to memory 3 during this period is eliminated surely.</p>
申请公布号 JPS5562589(A) 申请公布日期 1980.05.12
申请号 JP19780134786 申请日期 1978.10.31
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 FURUTA MASAO;IZUMI YOSHIHIRO;CHIHARA HIROMITSU;KAJIHATA IWAHO;HIRASE JIYUNICHI
分类号 G11C11/41;G06F1/26;G06F1/28;G11C5/14;G11C11/401;G11C11/414 主分类号 G11C11/41
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