发明名称 INSERTING AND DELECTING UNIT OF MEMORY CONTENTS
摘要 PURPOSE:To simplify a circuit by constituting the circuit with a RAM, a counter, two latch circuits, and an oscillator circuit which outputs four kinds of clock signal. CONSTITUTION:When the U/D input of counter 2 is set to H, counter 2 starts count-up from address 0 by reference clock signal CLK. First, storage contents of RAM1 which have been stored at address N where new data should be inserted are stored in latch circuit 3 by clock signal CLK1, and next, new data stored in latch circuit 5 is written at address N of RAM1 by clock signal CLK2, and storage contents of circuit 3 are transferred to circuit 2 and is stored by clock signal CLK3. After that, next signal CLK is inputted to the counter, and the address designated by counter 2 is updated to address N+1 to repeat the similar operation, thus inserting new data at address N. Next, in case of deletion of data at address N, the U/D input is set to L to cause counter 2 to count down, and the similar operation is repeated for every input of signal CLK.
申请公布号 JPS5562574(A) 申请公布日期 1980.05.12
申请号 JP19780134835 申请日期 1978.10.31
申请人 MATSUSHITA ELECTRIC WORKS LTD 发明人 KITAMURA MASAHIKO;HATAKAWA MAMORU
分类号 G06F12/06;G06F12/00;G11C7/00;(IPC1-7):11C7/00 主分类号 G06F12/06
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