| 摘要 |
A synchronous demultiplexer at a receiving station of a TDM/PCM telecommunication system, operating on an incoming bit stream organized in frames of 32 time slots of eight bits each, comprises a pair of substantially identical random-access memories each having 32 cells loaded with consecutive octets in successive time slots of a frame period P' under the control of a writing-address generator, stepped by clock pulses CK' extracted from the bit stream, and unloaded at a similar but not exactly identical rate in successive time slots of a period P'' under the control of a reading-address generator, stepped by locally generated clock pulses CK''. Writing as well as reading addresses are fed to both memories simultaneously but the two memories are loaded in alternate frame periods P' and unloaded in alternate frame periods P'' under the control of selection signals in the form of two square waves respectively derived from clock pulses CK' and CK''. When the relative drift of these clock pulses causes an almost complete overlap of the loading and unloading periods of one of the memories, a logic circuit forming part of a control unit reverses one of these square waves to re-separate the two operations. |
