发明名称 PREPARATION OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To let a high resisting pressure bipolar transistor and I<2>L with high performance coexist, by etching a n<+>-layer selectively mounted onto a semiconductor substrate. CONSTITUTION:An n<+> epitaxial layer 2 is installed onto a p-type substrate 1 through n<+> buried layers 4, and an n<+>-layer 13 is manufactured. The layer 13 is etched by a mixed liquid of fluohydric acid, nitric acid, acetic acid and iodine, p<+> separation layers 3, an n-type collector layer 10 and n<+>-layers 11 are successively formed by using a SiO2 mask 12, p-type base layers 5, 6 and a p-type injector layer 7 are further mounted, an emitter layer 8 and a collector layer 9 are installed by n<+> diffusion and electrodes 14 are attached. Since this constitution can thin the thickness of an epitaxial layer of an I<2>L portion more than a bipolar transistor portion, an upward current amplification factor is improved as compared to conventional devices in an I<2>L gate circuit while a bipolar transistor remains as it is kept in high resisting pressure, and working speed is also bettered.
申请公布号 JPS5556642(A) 申请公布日期 1980.04.25
申请号 JP19780128600 申请日期 1978.10.20
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 FURUKAWA AKIHIKO
分类号 H01L21/8226;H01L21/761;H01L27/02;H01L27/082 主分类号 H01L21/8226
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