| 摘要 |
<p>A complementary type MOS transistor device is disclosed including a p-channel type MOS transistor having source, drain and gate regions (10, 12, 20) formed in the n-well region (6) which is formed in the surface area of a p-type semiconductor layer (4) and an n-channel MOS transistor having source, drain and gate regions (13, 14, 22) formed in said semiconductor layer (4). The semiconductor layer (4) is formed on an n-type semi-conductor body (2) and a reverse bias voltage is applied between the semiconductor layer (4) and the semiconductor substrate (2).</p> |
