| 摘要 |
PURPOSE:To modulate a PCM signal under no influence of the jitters of VTR by forming a regenerated PCM signal to be elongated of a synchronizing signal data signal and data discrimination signal and then by controlling a window gate through the discrimination signal. CONSTITUTION:Synchronizing signal separator circuit 21 separates a PCM signal having beeing regenerated by VTR and elongated into synchronizing signal 60 forming the PCM signal, a data signal following with a space part between, and data discrimination signal 68 at the head part of the data signal, and RF type FF is reset by signal 60 and set by signal 68. The set output of this FF is delayed by a fixed period of time by delay circuit 71 to close window gate 56, so that the PCM signal will stably by synchronized and demodulated, even at the time of the following-up decrease of PLL 50, when the jitters of VTR are generated by window pulses of a frequency N times as high as that of signal 60 outputted from PLL 50 by signal 60 before being elongated through a memory, etc. |
