| 摘要 |
The pulse generator is described in which a pair of storage registers are connected in parallel with one another and initially loaded such that a first of the registers has a substantially smaller unfilled capacity than the second register. A clock generator then feeds pulses equally to the two registers to progressively reduce the unfilled capacity of each register and when the first register has been filled a 'full' signal is generated which causes immediate reloading of the first register to the same initial capacity. A logic circuit connected to selected bit outputs of the first register generates a pulse, or a pulse pattern, during the time taken to fill the first register and when the second register has been filled a second 'full' signal inhibits the feeding of further clock pulses to the register. The total number of pulse cycles is therefore the ratio of the initially unfilled capacity of the second register to the unfilled capacity of the first register.
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