| 摘要 |
PURPOSE:To enable a memory unit, incapable of simultaneous write-read operation to provide the simultaneous write and read operations by controlling write-read access and latching operation for read signals by a timing signal corresponding to clocks. CONSTITUTION:When the output of timing generating circuit 28 is made high in level by a clock signal, memory contents corresponding to a read address of memory circuit 22 are read out by attaining access by read register 25 through change-over circuit 26 and supplied to read register 24 through latch circuit 23 put in a through state by the high-level output of circuit 28. When the output of circuit 28 is inverted at the halfway point of this clock signal, circuit 26 selects write address register 27 and put it in a latch state with circuit 23, so that data from write data register 21 will be written in circuit 22. By the next clock, the same operation is repeated and substantially-simultaneous write-read operation can be attained by using a memory unit which can not perform simultaneous write-read operation. |
