| 摘要 |
PURPOSE:To generate the select signal by the dummy cell select line a predetermined time delayed later than the data cell select line, thereby prevent the reversion of the potential relation of the data line in the simiconductor memory circuit of one element. CONSTITUTION:m of the memory cell select lines 11 and m pairs of data lines 12 and one element memory 13 at an intersecting point of them are provided. The pairs of the data lines are provided with the differential type information detecting circuit 14. To the data line, the dummy cell 15 and the dummy select line 16 are connected. The dummy select line 16 of the main memoty circuit constructed in the above mentioned manner is provided with the delay circuit 21, and by delaying the generation of the select signal of the dummy silect line later by a predetermined time than the memory cell select line, the conducting time of the dummy cell coincides with the conducting time of the memory cell. Accordingly, the memory cell and the dummy cell is connected electrically to the data line simultaneously. The reversing condition of the potential in the data line can be prevented from generating. |
