| 摘要 |
PURPOSE:To raise an integration rate by arranging a capacitor of adjacent memory cells above and under a standard potential electrode put on a common use. CONSTITUTION:A N-type impurity diffusion layer 221 and 222 formed on a P-type silicon substrate 1 forms a source region or a drain of transistor T21 and T22 and a data line. A N-type impurity diffusion layer 23 forms a source or a drain region of the transistor T22. A field diffusion layer film 24 and channel stopper 25 are serves to separate a pair of memory cells substantially. An inversion layer 28 is induced by an electrode 27 on the substrate surface immediately under it, a capacitor C21 is formed. A capacitor C22 is formed between an electrode 30 and electrode 27. A gate electrode 32 is arranged on an insulation film 33, and a word line 36 is connected through a contact hole 37 to the gate electrode. |
