| 摘要 |
PURPOSE:To obtain ease of timing design and high general-purpose application by constituting the titled circuit of a selection circuit selecting one output of an FF circuit of a ring counter, an inverting circuit inputting an output of the selected FF circuit to the 1st stage and a logical gate circuit combining the combination of >=1 outputs of the FF circuit and giving an output. CONSTITUTION:The ring counter circuit comprising shift registers, an exclusive OR circuit and an F/F circuit sampling its output are provided with selection circuits 25-28. The selection circuit 25 selects one of outputs of each FF circuit and feeds back it via an inverting circuit 37 to a shift-in signal. Which stage output is fed back is controlled freely. This is equivalent to increase/decrease freely the number of stages of the ring counter so as to vary the period of the output timing. Further, the selection circuits 26-28 control freely the selection of any stage output to the ring counter as the input of an exclusive OR circuit 29. That is, the time position and pulse width of the output timing signal are made variable.
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