| 摘要 |
PURPOSE:To reduce the variation in the charge transition amount due to the variation in the threshold voltage of MISFET, by independently providing MISFET introducing charges and MISFET flowing out charges. CONSTITUTION:At the write-in of information, the potential of the bit line BW is determined with the circuit A1, next the potential of the word wire WW is made to high level, the MISFET-QW in the memory unit MS is conducted, and charges flow from the bit wire BW to the capacitor C. Further, at the readout of information, the word wire WR is made to high level, MISFET-QR is conducted, the storage charge of the capacitor C is distributed to the capacitor C1 of the bit wire BR, and the charge is read out at the circuit A2. |
