发明名称 FAILLSAFE LOGIC CIRCUIT
摘要 PURPOSE:To remove operation unstableness at the time of actuation by securing fail and safe completeness by connecting a logic converter circuit, which generates a constant level output by being supplied with a negative polarity voltage or positive polarity voltage excluded from an input, in series to a feedback circuit. CONSTITUTION:NOT circuit T is inserted into the feedback circuit and feeds NOT AS or OS of output AS or CS of basic logic circuits OR back to the input of basic logic circuit A1. Here, inputting a negative-polarity or positive-polarity voltage excluded from an input generates a constant-level output and NOT output -V equivalent to ''0'' is outputted corresponding to the input condition of circuit A1. With an input of direct current voltage -V equivalent to ''0'', oscillations start at a fixed threshold level and NOT output +V is developed. Consequently, the unstableness of starting operation can be removed with assurance of perfect fail and safe.
申请公布号 JPS5510280(A) 申请公布日期 1980.01.24
申请号 JP19780083416 申请日期 1978.07.08
申请人 NIPPON SIGNAL CO LTD 发明人 YODA MITSURU;AIHARA KOUICHI;NISHIMURA MITSUO
分类号 H03K19/007;(IPC1-7):03K19/007 主分类号 H03K19/007
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