发明名称 CLEARING SYSTEM FOR ERROR INFORMATION REGISTER
摘要 PURPOSE:To prevent the formation of infinite loop in advance, by outputting the signal clearing the error information register on the condition that no error is taken place for a given period through the provision of the delay circuit. CONSTITUTION:Based on the order signal taken place in mode selection, the content of the error information register 1 is set to the initial value to clear the register 1. In this case, the delay circuit 3 is provided, which sets the clear indication signal which is given based on the order signal and delays it for a given period. The circuit 3 outputs the clear signal clearing the register 1 on the condition that no error is taken place for a given period. Thus, the formation of infinite loop can be prevented in advance.
申请公布号 JPS559203(A) 申请公布日期 1980.01.23
申请号 JP19780079605 申请日期 1978.06.30
申请人 FUJITSU LTD 发明人 SAGARA HISAJIROU;AOKI TAKASHI
分类号 G06F11/14;G06F11/00;G06F11/34 主分类号 G06F11/14
代理机构 代理人
主权项
地址