| 摘要 |
A digital pipelined computer includes a memory (10) arranged to store high level language instructions and a plurality of microprogrammed digital computers (11, 12, 13, 14) coupled in parallel to the memory (10) and intercoupled by an interface (19) to form a pipeline for executing the high level language instructions. The interface (19) includes buffer register means (20-25) connected between selected pairs of the microprogrammed digital computers. When one of the microprogrammed digital computers attempts to load a full buffer register means or to read an empty buffer register means the computer initiating such attempt is temporarily halted. |
