发明名称 CYCLIC DATA TRANSMISSION SYSTEM, CYCLIC DATA TRANSMISSION/ RECEPTION EQUIPMENT AND CYCLIC DATA TRANSMITTING METHOD
摘要 <p>PROBLEM TO BE SOLVED: To immediately make the value of data on the side of reception coincident with a value on the side of transmission even when these data are omitted during the transmission by updating the value of a fixed length area only as for the fixed length area where the values are different between the data transmitted this time and the data transmitted the last time in accordance with a compared result for every fixed length area when the received sequence numbers are continued. SOLUTION: A processor 41 reads a value at the time of transmitting the data of that block the last time from a last transmission value buffer 52 of a main memory 42, compares that value with the value of data to be transmitted this time, namely, of data transferred to a transmission packet buffer 41 for the unit of a segment and discriminates the presence/absence of a change. According to the discriminated result, a bit map expressing the presence/absence of any change in the value of the segment is generated. Namely, when the value changes in the segment, '1' is set to a bit corresponding to that segment in the bit map and when there is no change in the value, '0' is set.</p>
申请公布号 JPH11252099(A) 申请公布日期 1999.09.17
申请号 JP19980049842 申请日期 1998.03.02
申请人 MITSUBISHI ELECTRIC CORP 发明人 TANAKA YASUHIRO;KUBO AKIHIKO
分类号 H04Q3/00;H04L1/08;H04L12/28;H04L12/70;H04L29/08;(IPC1-7):H04L12/28 主分类号 H04Q3/00
代理机构 代理人
主权项
地址