| 摘要 |
PURPOSE:To enable the data transmission high in reliability, by blocking the write- in of the three words received at the frame when the synchronizing word is present two or more times in one frame of the reception signal. CONSTITUTION:When all the bits of the synchronizing word at the second times enter the shift register SR during one frame of the reception signal, the AND gates AG.SYC produces the output 1 again, to cause output to the gate AG.F and to set FF2. The Q output of FF2 is given as the inhibit input of the AND gate AG.W controlling the write-in instruction timing signal to the reception data memory registers R11...R14, and even if the synchronizing word is mixed to the data word, it can completely be avoided with the operation of the additional circuits AG.F, FF2 and AG.W. Thus, by blocking the write-in to the three words for the reception data, the data transmission high in reliability can be made. |
