发明名称 DC Level clamping circuit
摘要 A DC level clamping circuit comprising a differential amplifier circuit constituted by a pair of transistors, a signal source, a first capacitor connected between the signal source and a first input terminal of the amplifier circuit, a second capacitor connected between the ground and a second input terminal of the amplifier circuit and having substantially the same capacity as the first capacitor, a pulse generator, a DC power source and first and second switching elements. The first switching element is connected between the DC power source and the first input terminal of the amplifier circuit, and the second switching element between the DC power source and the second input terminal of the amplifier circuit. These switching elements are controlled by the pulses from the pulse generator in a similar manner.
申请公布号 US4178558(A) 申请公布日期 1979.12.11
申请号 US19780945850 申请日期 1978.09.26
申请人 TOKYO SHIBAURA ELECTRIC CO LTD 发明人 MORIYAMA, HIDEKI;NAGASHIMA, YOSHITAKE;NOYORI, KAZUMASA
分类号 H04N5/18;H03F3/38;H03K5/007;(IPC1-7):H03F21/00 主分类号 H04N5/18
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