| 摘要 |
PURPOSE:To obtain an operation checking circuit for the shift register which converts the parallel data into the serial data. CONSTITUTION:With application of signal (b), shift register 1 takes in parallel data (a) of n-bit. In this case, if parity signal (f) of data (a) is ''1'', gate 2 delivers ''1'' to invert FF5 to the set state. Data (d) is delivered from register 1 with every application of signal (c) and then supplied to FF5 via gate 3 and 4. FF5 is inverted for its state only when data (d) is ''1''. In case the object device features the even parity and register 1 operates normally with no error, FF5 is reset finally. Before next parallel data (a) is taken into register 1, the state of FF5 is set to FF6. Thus, the malfunction of register 1 is detected by output (m). |
