摘要 |
<p>The system receives input pulse code modulated signals multiplexed in line to form sequential groups. The groups gi (i being a positive whole number) have n binary elements e.i.j. (j is a variable whole number from O n-1 for i fixed). The groups have a binary synchronising element which is such the eij and ei+1, have complementary binary values. The system has a circuit for memorising each binary element ei, j. It has a circuit for comparing each binary input element ei+1, j with each memorised binary element ei, j. A circuit marks each group gk+1 (k is a positive whole) having a single binary element ek+1, (1 is a whole between O and n-1) such that ei, 1 and ei+1 have complementary binary values whenever i is less than or equal to k. A circuit marks each binary element ek+2, 1.</p> |