PHASE COMPENSATION TYPE SYNCHRONIZING CIRCUIT

摘要

PURPOSE:To obviate the occurrence of the disturbance of synchronizing clock by providing a second phase difference memory circuit which transfers and stores the phase difference having been stored in a first phase difference memory circuit. CONSTITUTION:The phase difference storage signal (g) of a first phase difference memory device 15 is beforehand transferred to a second phase difference memory device 16. Here, the phase difference memory device 15 stores the next phase difference signal (d) and therefore it turns out that the contents having been stored in both phase difference memory devices 15 and 16 deviate by the peak shift quantity of the input signal (a). The phase difference memory signals (g) and (h) of both are operated of their difference by a subtractor 13 and the output (k) having undergone phase difference compensation is applied to an adder-integrator 12. Then, the input quantity of the adder-integrator 12 becomes the waveform being a+j+k. This compensation enables the disturbance of the voltage control oscillator 13 caused by the peak shift to be simultaneously compensated.