发明名称 TELEVISION SCREEN DISPLAY UNIT
摘要 PURPOSE:To enable only a chrominance sub-carrier oscillation circuit to fetch both the clock signal and horizontal synchronizing signal of a central processing unit CPU, by fetching the fixed horizontal synchronizing signal by stopping the central processing unit CPU from operating for (b) clocks by a gate signal. CONSTITUTION:In a television screen display unit composed of an information processing method including CPU14, read-only memory ROM and random access memory RAM, a clock signal for operating CPU14 is generated by oscillator 19 on the basis of the output of a chrominance sub-carrier oscillation circuit. In order to obtain Ts=aTc+bTc (a and b are positive integers) when the period of the clock signal is denoted by Tc with that of a horizontal synchronizing signal denoted by Rs meeting the broadcast standard requirements, the gate signal is applied from gate generating circuit 30 to CPU14 for bTc from the horizontal synchronizing signal from counter 20 and CPU14 is stopped from stopping for (b) clocks, thereby extracting the fixed horizontal synchronizing signal.
申请公布号 JPS54122033(A) 申请公布日期 1979.09.21
申请号 JP19780029409 申请日期 1978.03.15
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 MATSUSHITA AKIRA
分类号 H04N7/18;A63F9/00;A63F13/00;G06F3/14;G06F3/153;G09G5/00;G09G5/02;G09G5/04;G09G5/18;H04N9/00 主分类号 H04N7/18
代理机构 代理人
主权项
地址