| 摘要 |
PURPOSE:To secure an automatic simulation by feeding the control signal generated from the control unit back to the simulator. CONSTITUTION:The simulation signal interprets given process model 6 via scheduler 8 and then executes the process of the logic to write the result into schedule file 12 at the same time to deliver the process signal to control unit 3. On the other hand, unit 3 receives the process signal and then transmits the control signal to control signal receiver 10. The data obtained from the control signal is interpreted by data rewriting unit 11 to rewrite file 12 to process model 6. File 12 regulates the state of the next simulation to be used indirectly as the next execution state for the element within the process model when model 6 is interpreted. |
