发明名称 BIAS CIRCUIT
摘要 PURPOSE:To prevent the leak of the input signal from the bias line by using the SEPP emitter follower circuit to the bias power source and also to decrease the number of the capacitor to be suited for the integration. CONSTITUTION:The 1st reference voltage V1 features as V1 = VBE + VCC/2 with the forward voltage of the diode set to VBE. As voltage follower G is connected to V1, V1 = V2 is obtained. Accordingly, bias voltage Vref drawn out from the SEPP emitter follower becomes as Vref1 = Vref2 = V2 - VBE = VCC/2, obtaining just the half value of power voltage VCC. As output resistance ROUT is extremely low for the SEPP emitter follower, the leak of the input signal of amplifier A1 to the bias line receives the sufficient attenuation of ROUT/RB1. As a result, the isolation can be improved extremely for the input signal.
申请公布号 JPS54114157(A) 申请公布日期 1979.09.06
申请号 JP19780021775 申请日期 1978.02.27
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 ISHII JIYUN
分类号 H03F1/30;H03F3/20;H03F3/213;H03F3/30 主分类号 H03F1/30
代理机构 代理人
主权项
地址