| 摘要 |
PURPOSE:To ensure the accurate reading of the data at the receiving side by obtaining the addition average for the jitter of the received data and then regenerating the steady clock signal based on the result of the average addition to secure the synchronization again and then to transmit the data. CONSTITUTION:Digital reception data A is supplied to displacement point detector 21 from terminal 20 to detect the rise and fall of data A. Thus, clock information pulse B is generated and then sent to phase comparator 22 to be compared with division reference signal C, and phase difference pulse D is delivered according to the phase difference. This output is then integrated in sequence at adder 26 of binary n-bits and introduced to ratch circuit 28 to calculate (27) pulse B, and the phase difference addition average value of pulse B is ratched by output E of the frequencies with which the jitter effect can be ignored. Then the pulse at the displacement point of pulse B is supplied to divider 24 from one-shot pulse generator 30. In this way, the steady clock signal is regenerated to secure the synchronization again, and the data is transmitted to be read out accurately at the receiving side. |
