| 摘要 |
A charge-coupled device (CCD) multiplying digital-to-analog converter multiplies a bipolar analog signal, representing as a charge, by a digital word, and produces a four-quadrant analog product, also represented as a charge. An analog signal S is added to or subtracted from a bias, resulting in signals S+B and -S+B, which are converted into corresponding positive charges, QS+QB and -QS+QB, which are transferred into potential wells at Xi and Yi, respectively. A digital word may be represented as b1b2b3 . . .bN, where N is the word length. The CCD converter comprises N parallel devices, each of which performs the function of multiplying the signal S by either 0 or 1/2i. A gate between Xi and Yi is controlled by the binary bit bi. Equilibration occurs or does not occur depending on whether bi equals 0= or 1. The charges left in Xi and Yi are then transferred to two other potential wells, which have channel stops diffused into them. The charges in the outer portions in each well are dumped to ground, while the remaining charges in each of the N devices are summed in a common potential well, to form a product as a sum of terms.
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