| 摘要 |
PURPOSE:To enable the control of the frequency shift amount over a wide range and in a low-speed operation for the synthesizer receiver or the like by securing the selective combination of the pulse sampling control circuit and the fixed divider for the PLL. CONSTITUTION:Pulse sampling control circuit 13 and 23 are provided to the PLL along with fixed divider M114 and M224, and circuit 13 and 24 are set under the operation and non-operation states by switch S1 and S2 respectively. Through the selectively combined action between S1 and S2, the output pulse given from divider 12 is sampled optionally and the output of variable divider 15 varies accordingly. As a result, the operation step frequency of the PLL can be shifted, thus ensuring a wide-range control of the frequency shift amount with the reduced switching times. |
