发明名称 DIGITAL DELAY CIRCUIT
摘要 PURPOSE:To control a delay in an IC with high accuracy by connecting plural delay means each outputting either a signal through a logic gate or a signal not therethrough in series and allowing each state to select a signal passing through the logic gate or a signal not therethrough. CONSTITUTION:With a high level signal applied to a terminal S1 and a low level signal applied to terminals S2, S3, a circuit B1 is turned off in a delay means 1a and an input signal passes through an AND circuit A1 via a logic gate 2a comprising 2 stags of NOT circuits, then a delay of 2taupd is caused. With a high level signal applied to the terminals S1,S2 and a low level signal to the terminal S2, circuits A1, A2 are turned on and circuits B1, B2, B3 are turned off, a signal is subjected to a delay of 6taupd. Thus, the delay is varied over a wide range and a desired delay is obtained.
申请公布号 JPH0263211(A) 申请公布日期 1990.03.02
申请号 JP19880214383 申请日期 1988.08.29
申请人 YOKOGAWA ELECTRIC CORP 发明人 UCHIDA AKIRA;ODAKA HIROHISA;YAGIHARA TAKESHI;MIURA AKIRA
分类号 H03K5/13;H03K5/133 主分类号 H03K5/13
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