发明名称 |
SELF-ALIGNED CMOS PROCESS FOR BULK SILICON AND INSULATING SUBSTRATED CE |
摘要 |
<p>The method for fabrication of a self-aligned gate CMOS structure which employs no additional masking steps as compared to the standard CMOS fabrication process, this improved process providing the advantages of self-alignment between the N+ and P+ source and drain diffusions with respect to their gate regions, and metal contact openings which do not overlap the edges of the P+ or N+ source and drain regions. The self-aligning gate region is defined by a silicon nitride gate layer. Several embodiments of the novel process are described.</p> |
申请公布号 |
CA1057416(A) |
申请公布日期 |
1979.06.26 |
申请号 |
CA19780317207 |
申请日期 |
1978.12.01 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
SPADEA, GREGORIO |
分类号 |
(IPC1-7):01L21/72;01J17/00 |
主分类号 |
(IPC1-7):01L21/72 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|