| 摘要 |
PURPOSE:To unify the circuit constitution of the binary counter with use of IGFET with easiness and thus to facilitate the formation of the counter into an IC. CONSTITUTION:The 3rd inverter 111 and 121 are formed between clock inverter 11C1 and 12C1 to secure the continuous operation. And IGFET19 and 20 are used for the 1st stability circuit to form 5th clock inverter 13C1, and FET21 and 22 are used for the 2nd stability circuit to form 6th clock inverter respectively. In such structure, an identical distribution and the form can be secured for all circuit elements since no coupling FET is used, and thus the gate output becomes uniform to the drain output. Thus, the designing can be ficilitated. Inverter 11C1 and 12C1 supply the charge to be memorized temporarily at point a' and b' through the 1st and 2nd stability circuits respectively at the non- operation time, with no attenuation caused. Thus, the binary counter can be used at the low frequency. |
