| 摘要 |
A memory apparatus which serves as an interface apparatus between an alarm system and a computer, whereby alarm signals from the alarm system each containing as its content a class of alarm, e.g., a fire, burglary or absence alarm or the location of an alarm, are introduced into the relatively large computer so as to display the alarms or control the operation of various disaster preventive units. The memory apparatus comprises a plurality of memory circuits connected in cascade and each adapted to store an alarm signal, a plurality of flip-flop circuits for shifting the memory content from the input side memory circuit into the output side memory circuit, a drive circuit for sequentially actuating the flip-flop circuits and a halting circuit for stopping the operation of the drive circuit. When the alarm signal is shifted sequentially so that it is eventually stored in the final-stage memory circuit, the alarm signal is in readiness for reading through the output terminals by the computer which in turn will be interrupted to read in the alarm signal when it is idle or ready to work on the alarm signal. After the interruption has been completed, the memory content of the memory circuit just preceding the final stage is shifted into the final-stage memory circuit, and in this way the alarm signals are sequentially introduced into the computer by interruption in the order of the first signal, second signal, third signal and so on. The storage capacity of each memory circuit needs not be greater than that required to store each alarm signal, and also the read time required for the computer upon each interruption is reduced to that required for reading only the content of the final-stage memory circuit or the time required to read the number of bits corresponding to one alarm signal. |
