| 摘要 |
PURPOSE:To reduce the noise generated at the leading edge and the trailing edge of signals outputted from a logical operation circuit, by delaying the input of each logical operation circuit in order by minute time and generating the rise time and the breaking time longer than the regular rise time and breaking time of signals in appearance. CONSTITUTION:Logical operation circuit 1 is constituted by n-number logical operation circuits 2, (n-1)-number delay elements 3 and control circuit 6 which controls the output signal level of each circuit 2 to 1/n of the regular level, and the input of each circuit 2 is inputted while being delayed in order by a minute time according as the operation of circuits 2 is moved from the left to the right by elements 3. Therefore, when circuit 2 is driven, the rise time and the breaking time longer, in appearance, than egular rise time and breaking time of output signals outputted onto signal line 4 are generated, and signals having the same level as regular output signals are synthesized and outputted. As a result, the noise generated at the leading edge and the trailing edge of output signals of circuit 2 can be reduced. |
