| 摘要 |
PURPOSE:To increase the capacitor capacitance while reducing the element area, by forming the capacitor on the tilt surface provided on the surface of the semiconductor substrate, in the memory cell consisting of each one of MIS type transistor and capacitor. CONSTITUTION:The N<+> type region 2' being the digit line of the drain in common use of memory cell of MIS type element is formed by diffusion on the P type Si substrate 1', and the concave of V-shaped type is formed by selective etching on the surface of the substrate 1' remote from this. Next, on the surface of the concave, the capacitor insulation film 5' is coated, and the gate insulation film 5' is formed by surrounding it. After that, the N<+> type polycrystal Si film 6' being the capacitor electrode, between layer insulation layer 7; and the N<+> type polycrystal layer 8' being the address line of gate electrode in common use of memory cell are coated by lamination on the film 5'. Thus, the sum of the insulation film capacitance betweed the capacitor electrode 6' and the N type inverting layer 3' caused with the application of the voltage VDD and the depletion layer capacitance between the inverting layer 3' and the substrate 1' is used as capacitor capacitance. |
