| 摘要 |
<p>PURPOSE:To make it possible for a processor, which becomes a master, to control effectively a processor, which becomes a slave, by the suspension of executing instructions and the firmware interrupt of the interrupted processor. CONSTITUTION:Plural processors are connected to system bus 1, and processor ACU2 which becomes a master causes the interrupt to processor ACU3 which becomes a slave. Then, processor ACU3 suspends executing instructions to cause a firmware interrupt and checks the status by firmware to recognize the start. Then, ACU3 leads the program counter address, which is started by slave ACU, from the parameter transfer area and starts the program to perform a prescribed operation according to contents of the status and the parameter area at this time. As a result, master processor 2 can control effectively slave processor 3.</p> |
