| 摘要 |
PURPOSE:To shorten the length of the coefficient word of a multiplier, by providing a circuit integrating a signal to the output part or feedback part of a digital filter narrow in pass band and in stop band which operate at a sampling frequency much higher than the pass band. CONSTITUTION:An integrating circuit is provided newly to the digital filter circuit composed of delay element 1, multipliers 40 to 45, and adder 3. Namely, in order to obtain y(nT) satisfying equation (6) using input signal x(nT) of the filter, output signal y(nT), and numeral u(nT) obtained from y(nT), the integrating circuit composed of adder 6, delay element 1, and multipliers 51 and 52 are connected to output u(nT) of adder 3 of the filter. As a result, the coefficient of acyclic filter FIR becomes a difference in coefficient of multiplier MPL of original FIR, so that the coefficient of MPL can be realized by using a small number of bits. |
