| 摘要 |
1494491 Compensation circuit and pulse generator HITACHI LTD 15 Jan 1975 [16 Jan 1974] 2105/74 Heading H3T A compensation circuit 23 used in combination with IGFET pulse generator circuit 22 comprises an FET 19 whose drain is connected to the gates of IGFETS 12, 14 the gate of the FET 19 being connected to bias voltage. Variations in the pulse generator circuit 22 due to temperature; or MOSIC constructional variations, all the FET's being fabricated conjointly; are thus compensated. The FET 19 may be of the depletion type, the gate being coupled to ground, the resistor 21 possibly being separately manufactured, or of the enhancement type, the gate being coupled to supply V GG , in which case compensation additionally takes place for supply voltage variations. The gate of FET 19 may be connected to the junction between resistor 21 and its own drain. The compensation circuit may comprise a pair 19, 20 of FET's, or p-channel enhancement, p-channel depletion, respectively types. Circuit 11, 12 is the first inverter of a sequence of three, 11, 12; 13, 14; 15, 16, p-channel enhancement IGFETS 11, 13, 15 being connected in a ring to form the pulse generator circuit 22, changeover delay capacitors 17, 18 being provided, load IGFET's 12, 14, 16 being of the depletion type. The MOSFETS of the combination 22, 23 are all fabricated on one monocrystalline Si MOSIC chip, with externally connected resistor, and capacitors 21, 17, 18. The compensation, as applied to the pulse generator circuit, additionally compensates for pulse period, and mark/space, variations. |
