| 摘要 |
A frequency divider (1), a seconds counter (2), a minutes counter (3), an hours counter (4), a date counter (5) and a month counter (6) are connected in a cascade. The frequency divider (1) generates a pulse of 1 Hz. This 1 Hz pulse is fed to the counters (2, 3, 4, 5 and 6). The counter content of the counters (2 to 6) is fed to a decoder circuit (8). As a function of a signal MDD for the type of month/date display and a signal HMD for the type of hour/minute display or a signal SD for the type of seconds display, the decoder circuit (8) receives from a control circuit (7) for the mode of operation month/date display signals from the counters (6 and 5), hours/minutes display signals from the counters (4 and 3), or a seconds display signal from the counter (2), in order to generate a decoded signal corresponding to the received signal. In the case of execution of a time correction, the control circuit (7) for the mode of operation supplies a signal SZ, MIS, HS, DS or MOS for the type of time setting to a specific counter of the counters (2 to 6), only this specific counter being put into a time correction state. The control circuit (7) for the mode of operation has a first and a second switch, the circuit (7) having two circuit sections for determining the operating states of these switches, so that when a switch is actuated either a time setting signal or a signal for the type of display is generated. <IMAGE>
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