| 摘要 |
A digital shift register comprises a series of substantially identical bistable circuits each of which has a signal input, a reference level input, an output, and a clock signal input. Each signal inputs of the second and subsequent bistable circuits of the series is connected to the output of the preceding bistable circuit and each reference level input is coupled to a common reference potential point. The register also includes means for driving the clock signal inputs of each pair of adjacent bistable circuits in the series alternately with current pulses under the influence of a clock signal.
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