| 摘要 |
A circuit for converting a diphase signal into an isochronous baseband data signal, operates by extracting a clock signal from the carrier signal and combining the diphase signal and clock signal in a modulo-2 adder. The clock signal has a frequency equal to the reciprocal of the duration of one element of the baseband data and is derived by isolating a second harmonic of the carrier signal and applying it to a frequency halving circuit. The relative phase of the clock signal and the isochronous baseband signal is monitored at discrete intervals. If there is a phase error on consecutive occasions, caused by the ambiguity in the phase of the clock signal, the relative phase of the clock signal to the isochronous baseband data signal is shifted by 180 DEG . |
